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Figure 16.14. USART SmartCard Stop Bit Sampling
P
1/2 stop bit
NAK or stop
Stop
13 14 15 16 1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 X
X
X
X
X
X
7
8
1
2
3
4
5
6
7
8
9
10
X
X
6
1
2
3
4
5
6
7
8
x
4
1
2
3
4
5
x
For communication with a SmartCard, a clock signal needs to be generated for the card. This clock
output can be generated using one of the timers. See the ISO 7816 specification for more info on this
clock signal.
SmartCard T1 mode is also supported. The T1 frame format used is the same as the asynchronous
frame format with parity bit enabled and one stop bit. The USART must then be configured to operate
in asynchronous half duplex mode.
16.3.3 Synchronous Operation
Most of the features in asynchronous mode are available in synchronous mode. Multi-processor mode
can be enabled for 9-bit frames, loopback is available and collision detection can be performed.
16.3.3.1 Frame Format
The frames used in synchronous mode need no start and stop bits since a single clock is available to
all parts participating in the communication. Parity bits cannot be used in synchronous mode.
The USART supports frame lengths of 4 to 16 bits per frame. Larger frames can be simulated by
transmitting multiple smaller frames, i.e. a 22 bit frame can be sent using two 11-bit frames, and a 21
bit frame can be generated by transmitting three 7-bit frames. The number of bits in a frame is set using
DATABITS in USARTn_FRAME.
The frames in synchronous mode are by default transmitted with the least significant bit first like in
asynchronous mode. The bit-order can be reversed by setting MSBF in USARTn_CTRL.
The frame format used by the transmitter can be inverted by setting TXINV in USARTn_CTRL, and the
format expected by the receiver can be inverted by setting RXINV, also in USARTn_CTRL.
16.3.3.2 Clock Generation
The bit-rate in synchronous mode is given by Equation 16.3 (p. 193) . As in the case of asynchronous
operation, the clock division factor have a 13-bit integral part and a 2-bit fractional part.
USART Synchronous Mode Bit Rate
br = f HFPERCLK /(2 x (1 + USARTn_CLKDIV/256))
(16.3)
Given a desired baud rate brdesired, the clock divider USARTn_CLKDIV can be calculated using
Equation 16.4 (p. 193)
USART Synchronous Mode Clock Division Factor
2011-04-12 - d0001_Rev1.10
193
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